Short Course

image
Michael Flynn,
Univ. of Michigan
9:00-17:00, Tuesday
26th July 2016
Room 326
UCD, Belfield Campus
Analog to Digital Conversion and ADC Based Interfaces
Course Content: Although analog-to-digital converters have existed for more than 70 years, new ADC techniques continue to emerge. ADC architectures are evolving to deliver higher performance and also to take advantage of improved process performance. This "one-day" short course reviews ADC architectures, discusses new techniques and shows new applications.
- The first part of the short course deals with successive approximation, or SAR, ADCs. The SAR ADC architecture is reviewed first. A noise-shaping scheme shapes comparator noise and quantization noise in a SAR to improve effective resolution. The capacitors in a SAR ADC can also be configured to filter the input. A highly reconfigurable radio is based on a filtering SAR ADC.
Pipeline ADCs were proposed 70 years ago and have long been a workhorse in mixed-signal design. After an overview of the pipeline architecture, the presentation reports on recent progress on pipeline ADCs. The benefits of combining SAR ADCs with pipeline ADCs will be discussed. A SAR-assisted pipeline ADC enables a very efficient two-stage pipeline by enabling a high first-stage resolution. In our recent work in 45nm SOI CMOS, a 9b 2GS/s ADC architecture interleaves a pair of two-stage SAR-assisted pipeline ADCs to achieve high performance with a shared low-gain op-amp and a shared low-accuracy 2nd stage sub-ADC.
- The second part of the discussion on pipeline converters reviews our recent work on ring-amplifiers as an alternative to OTAs in pipeline ADCs. The ring amplifier, introduced by Hershberg and Moon in 2012, is an intriguing alternative to the OTA, promising reduced power consumption as well as much smaller area. Our new ring amplifier structure, presented at ISSCC 2014, further improves the resilience and efficiency of the ring amplifier architecture. A 100MS/s, 10.5-bit, comparator-less pipeline ADC using self-biased ring amplifiers consumes only 2.46mW. Most recently our ISSCC 2015 design improves both resolution (11.5b ENOB) and efficiency (7fJ/conv.step).
- The third part covers compressive sampling and some ADC applications. Compressive sampling allows the number samples needed to digitize a signal to be reduced below the Nyquist limit. The tradeoffs of compressive sampling are discussed. Novel ADCs are an integral part of a brain-machine interface chip for treatment of Parkinson’s disease.
- The final section of the short course gives an overview of the Journal of Solid State Circuits (JSSC). The JSSC is the premier publication on integrated circuit design. After an overview of the Journal we will discuss the Journal’s submission and the review process. The overview will conclude with advice on how to write a good JSSC paper.
Speaker's Bio: Michael P. Flynn was born in Cork, Ireland. He received the BE and the M.Eng.Sc degrees from University College Cork (UCC) in 1988 and 1990, respectively and received the Ph.D. degree from Carnegie Mellon University in 1995. He was with National Semiconductor in Santa Clara, CA, from 1993 to 1995 and from 1995 to 1997 he was a Member of Technical Staff with Texas Instruments, Dallas, TX. During the four-year period from 1997 to 2001, he was with Parthus Technologies, Cork, Ireland. Dr. Flynn joined the University of Michigan in 2001 and is currently Professor. His technical interests are in data conversion, RF circuits, serial transceivers and biomedical systems. Michael Flynn is an IEEE Fellow and a 2008 Guggenheim Fellow. He is also Editor-in-Chief of the IEEE Journal of Solid-State Circuits.